The present invention relates to electronic circuits, and more particularly, to techniques for varying frequencies of periodic signals.
A high-speed digital data stream can be transmitted through a transmission line to a receiver without an accompanying clock signal. A phase-locked loop (PLL) circuit generates one or more clock signals from an approximate frequency reference signal, and then a clock and data recovery (CDR) circuit in the receiver phase-aligns the clock signals to the transitions in the data stream. The clock signals have different phases. The receiver uses the clock signals to sample bits in the data stream.
Some types of multi-channel CDR circuits have frequency divider circuits. The frequency divider circuits divide the frequencies of the clock signals generated by a phase-locked loop (PLL) circuit to generate frequency divided clock signals having lower frequencies than the clock signals generated by the PLL circuit. The frequency divided clock signals enable the receiver to support 2 different data rates of an incoming data stream without using an additional phase-locked loop.
FIG. 1 illustrates an example of a prior art bypass/frequency divider system 100. System 100 includes 8 bypass/frequency divider (B/FD) circuits 101-108 that generate 8 periodic output clock signals PHOUT0, PHOUT1, PHOUT2, PHOUT3, PHOUT4, PHOUT5, PHOUT6, and PHOUT7 (i.e., PHOUT0-PHOUT7) at their respective O outputs based on 8 periodic input clock signals PH0, PH1, PH2, PH3, PH4, PH5, PH6, and PH7 (i.e., PH0-PH7), respectively.
B/FD circuits 101-108 receive enable signals ENABLE0, ENABLE1, ENABLE2, ENABLE3, ENABLE4, ENABLE5, ENABLE6, and ENABLE7 (i.e., ENABLE0-ENABLE7), respectively, at their A inputs. B/FD circuits 101-108 receive control signal BYPASS at their B inputs. B/FD circuits 101-104 receive enable signal EN at their C inputs. Inverter 110 inverts a power down (PD) signal to generate the enable signal EN.
System 100 also includes D flip-flop storage circuits 111-114. A ground signal VSS is provided to the D inputs of flip-flops 111-114. The PD signal is provided to the P (preset) inputs of flip-flops 111-114. The PH1, PH3, PH5, and PH7 input clock signals are provided to the clock inputs of flip-flops 111-114, respectively. Flip-flops 111-114 generate enable signals EN4-EN7, respectively, at their QN outputs. Enable signals EN4-EN7 are provided to the C inputs of B/FD circuits 105-108, respectively. Each of flip-flops 111-114 generates complementary digital signals at its Q and QN outputs.
B/FD circuits 101-108 receive clock signals PH0-PH7 at their BYPASSCLK inputs, respectively. B/FD circuits 101-108 receive clock signals PH0, PH2, PH4, PH6, PH0, PH2, PH4, and PH6 at their DIVCLK inputs, respectively.
FIG. 2 illustrates a prior art bypass/frequency divider (B/FD) circuit 200 that is in each of the B/FD circuits 101-108. B/FD circuit 200 includes NAND logic gates 201-205, inverters 211-216, D flip-flop 210, and NOR logic gate 220. When the signals at the A and B inputs of B/FD circuit 200 (i.e., BYPASS and one of ENABLE0-ENABLE7) are both in logic high states, and the signal at the C input of B/FD circuit 200 is in a logic low state (i.e., one of EN and EN4-EN7), B/FD circuit 200 is in bypass mode. In bypass mode, the output signal of inverter 211 is in a logic high state, and the output signal of NAND gate 203 is in a logic high state. The output of NAND gate 203 is coupled to the P input of flip-flop 210. A logic high state at the P input of flip-flop 210 holds the signal at the QN output of flip-flop 210 in a logic low state, causing the output signal of NAND gate 204 to be in a logic high state. As a result, B/FD circuit 200 passes the clock signal at the BYPASSCLK input to the O output in bypass mode without an inversion through NAND gates 201 and 205 and inverters 215-216. Flip-flop 210 generates complementary digital signals at its Q and QN outputs.
When the signals at the A and C inputs of B/FD circuit 200 are in logic high states, and the signal at the B input of B/FD circuit 200 is in a logic low state, B/FD circuit 200 is in frequency divider mode. In frequency divider mode, B/FD circuit 200 divides the frequency of the clock signal at its DIVCLK input by 2 to generate a frequency divided clock signal at its O output. In frequency divider mode, the output signal of NAND 203 is in a logic low state, which does not hold the signal at the QN output of flip-flop 210 in a preset logic state. Inverter 214 is coupled between the Q output and the D input of flip-flop 210. The DIVCLK input of circuit 200 is coupled to the clock input of flip-flop 210. In frequency divider mode, the signal at the QN output of flip-flop 210 toggles between logic high and logic low states at each rising edge of the clock signal received at the DIVCLK input of circuit 200. Thus, the clock signal at the QN output of flip-flop 210 has one-half the frequency of the clock signal at the DIVCLK input of circuit 200. The output signal of NAND gate 201 is in a logic high state, and the output signal of inverter 213 is in a logic high state. As a result, the clock signal at the QN output of flip-flop 210 passes to the O output of circuit 200 through NAND gates 204-205 and inverters 215-216 without an inversion in frequency divider mode.
FIG. 3 is a timing diagram that shows waveforms of the input clock signals PH0-PH7 of system 100. FIG. 3 shows the relative phases of PH0-PH7. Input clock signals PH0-PH7 have relative phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively.
FIG. 4 is a timing diagram that shows waveforms of the BYPASS control signal and the output clock signals PHOUT0-PHOUT7 of system 100. In bypass mode, the BYPASS signal is in a logic high state, and the ENABLE0-ENABLE7 signals are all in logic high states. In bypass mode, B/FD circuits 101-108 pass input clock signals PH0-PH7 from their respective BYPASSCLK inputs to their respective O outputs as output clock signals PHOUT0-PHOUT7, respectively, as described above with respect to FIG. 2. Output clock signals PHOUT0-PHOUT7 have the same frequencies as input clock signals PH0-PH7, respectively, in bypass mode.
Each of the B/FD circuits 101-108 enters frequency divider mode after the BYPASS signal at its B input transitions from a logic high state to a logic low state and the signal at its C input is in a logic high state. The EN4-EN7 signals at the C inputs of B/FD circuits 105-108 transition to logic high states after the first rising edges of signals PH1, PH3, PH5, and PH7, respectively, that occur after the PD signal transitions to a logic low state. The ENABLE0-ENABLE7 signals remain in logic high states in frequency divider mode.
As shown in FIG. 4, the output clock signals PHOUT0-PHOUT7 of system 100 do not have the ideal relative phase offsets of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively, in frequency divider mode. Instead, after a falling edge in the BYPASS signal, the rising edges of the frequency divided clock signals PHOUT4-PHOUT7 are approximately aligned with the rising and falling edges of the frequency divided clock signals PHOUT0-PHOUT3, respectively, as shown in FIG. 4. In addition, the falling edge in the BYPASS signal causes glitches in output clock signals PHOUT2-PHOUT5 in FIG. 4.